Especificações Técnicas

OUTROS PART NUMBERS PARA ESTE COMPONENTE: 74HCT259, MM74HC259M THE 74HC259; 74HCT259 IS AN 8BIT ADDRESSABLE LATCH. THE DEVICE FEATURES FOUR MODES OF OPERATION. IN THE ADDRESSABLE LATCH MODE, DATA ON THE D INPUT IS WRITTEN INTO THE LATCH ADDRESSED BY THE INPUTS A0 TO A3. THE ADDRESSED LATCH WILL FOLLOW THE DATA INPUT, NONADDRESSED LATCHES WILL RETAIN THEIR PREVIOUS STATES. IN MEMORY MODE, ALL LATCHES RETAIN THEIR PREVIOUS STATES AND ARE UNAFFECTED BY THE DATA OR ADDRESS INPUTS. IN THE 3TO8 DECODING OR DEMULTIPLEXING MODE, THE ADDRESSED OUTPUT FOLLOWS THE D INPUT AND ALL OTHER OUTPUTS ARE LOW. IN THE RESET MODE, ALL OUTPUTS ARE FORCED LOW AND UNAFFECTED BY THE DATA OR ADDRESS INPUTS. INPUTS INCLUDE CLAMP DIODES. THIS ENABLES THE USE OF CURRENT LIMITING RESISTORS TO INTERFACE INPUTS TO VOLTAGES IN EXCESS OF VCC.   FEATURES AND BENEFITS WIDE SUPPLY VOLTAGE RANGE FROM 2.0 V TO 6.0 V LATCHUP PERFORMANCE EXCEEDS 100 MA PER JESD 78 CLASS II LEVEL B COMPLIES WITH JEDEC STANDARDS: JESD8C (2.7 V TO 3.6 V) JESD7A (2.0 V TO 6.0 V) COMBINED DEMULTIPLEXER AND 8BIT LATCH SERIALTOPARALLEL CAPABILITY OUTPUT FROM EACH STORAGE BIT AVAILABLE RANDOM (ADDRESSABLE) DATA ENTRY EASILY EXPANDABLE COMMON RESET INPUT USEFUL AS A 3TO8 ACTIVE HIGH DECODER INPUT LEVELS: FOR 74HC259: CMOS LEVEL FOR 74HCT259: TTL LEVEL ESD PROTECTION: HBM: ANSI/ESDA/JEDEC JS001 CLASS 2 EXCEEDS 2000 V CDM: ANSI/ESDA/JEDEC JS002 CLASS C3 EXCEEDS 1000 V MULTIPLE PACKAGE OPTIONS SPECIFIED FROM 40 C TO 85 C AND FROM 40 C TO 125 C 74HC259D CI 74HC LATCHES CMOS LOGIC SERIES 6V SOIC-16 MAIORES DETALHES DE 74HC259D NO SITE DO FABRICANTE: HTTPS://ASSETS.NEXPERIA.COM/DOCUMENTS/DATA-SHEET/74HC_HCT259.PDF TAGS DE 74HC259D: 74HC259, 74HC259D, 74HCT259, MM74HC259M, 74HC259BQ, 74HC259D, 74HC259PW, 74HCT259BQ, 74HCT259D, 74HCT259PW

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